Video display devices (e.g., projectors) which receive a plurality of types of video signals (RGB signals, YCbCr signals, or video signals having different resolutions) determine the types and resolutions of video signals input thereto, and switch to an optimum image processing process depending on the determined types and resolutions to display images. The types and resolutions of video signals are determined by a process disclosed in Patent document 1, for example.
RGB signals include color signals of three primaries R (red), G (green), and B (blue), and a plurality of types of synchronizing signals. YCbCr signals include a Y (luminance) signal, a Cr (R−Y) color difference signal, a Cb (B−Y) color difference signal, and a plurality of types of synchronizing signals.
There are known a number of modes representative of the resolutions of video signals, e.g., VGA, SVGA, XGA, WXGA, SXGA, SXGA+, WSXGA, +UXGA, WUXGA, QXGA, etc.
FIG. 1 is a block diagram showing the arrangement of a video display device according to the background art. The video display device shown in FIG. 1 is of the arrangement disclosed in Patent document 1 described above.
As shown in FIG. 1, the video display device according to the background art includes A/D converter 1, signal discriminating and monitoring circuit 2, scaler circuit 3, CPU 4, panel drive circuit 5, and display panel 6.
A/D converter 1 converts video signals including synchronizing signals, input from a computer and various video reproducing devices, into digital signals.
Signal discriminating and monitoring circuit 2 separates a horizontal synchronizing signal and a vertical synchronizing signal from a video signal input thereto (hereinafter referred to as “input video signal”), detects various information required to determine the type and resolution of the input video signal from the horizontal synchronizing signal and the vertical synchronizing signal, and outputs the detected information to CPU 4. Some video display devices include a synchronizing separator, not shown, for separating a horizontal synchronizing signal and a vertical synchronizing signal from a video signal and supplying them to signal discriminating and monitoring circuit 2.
The information detected by signal discriminating and monitoring circuit 2 includes a horizontal synchronizing frequency, a vertical synchronizing frequency, a total number of lines, a synchronizing polarity (Nega or Posi), a synchronizing type (Sep(horizontal and vertical frequencies), CS (Composite Sync) or Sync on G (green signal synchronization), Tri Sync (Tri-level Synchronization), a scan type (Interlaced or Non-Interlaced), a vertical synchronizing width, a number of effective video lines, etc.
CPU 4 determines whether or not an input video signal has changed, and the type and resolution of an input video signal after it has changed, using the information detected by signal discriminating and monitoring circuit 2, and makes various required settings according to an image processing sequence which corresponds to the input video signal, based on the determined results. Parameters that are set by CPU 4 include, for example, the frequency-dividing ratio and phase of a PLL circuit (not shown) for generating a clock signal for use in A/D converter 1, resolution converting data for use in scaler circuit 3, the aspect ratio of a displayed image, a color system, etc.
Scaler circuit 3 converts the resolution of the input video signal into the resolution of display panel 6 according to the parameters set by CPU 4, generates a video display signal for displaying video images on display panel 6, and outputs the video display signal to panel drive circuit 5.
Signal discriminating and monitoring circuit 2 and scaler circuit 3 can be implemented by an LSI comprising a memory and various logic circuits, a CPU or the like for executing processing sequences according to programs, or the like.
Panel drive circuit 5 forms a video image on display panel 6 according to a video display signal output from scaler circuit 3. The video image formed on display panel 6 is projected onto a screen or the like by a projection optical system, not shown, including a light source, for example.
If the video display device is a direct-view-type display device, then display panel 6 comprises an LCD (Liquid Crystal Display), for example. If the video display device is a projection-type display device, then display panel 6 comprises DMD (Digital Mirror Device), for example.
As shown in FIG. 1, scaler circuit 3 includes frame memory 31, video input section 32, resolution converter 33, video output section 34, synchronization switch 35, and synchronizing signal generating circuit 36.
Frame memory 31 temporarily stores the data of successively input video signals (hereinafter referred to as “video data”) frame by frame. Frame memory 31 has a memory capacity large enough to store 3 or more frames of video data. Video data are stored frame by frame in frame memory 31 by video input section 32. After the resolution of the video data is converted by resolution converter 33, the video data are output as a video display signal to panel drive circuit 5 by video output section 34.
At this time, synchronization switch 35 supplies video output section 34 with either a vertical synchronizing signal separated from the input video signal or a panel vertical synchronizing signal (60 Hz) which is asynchronous with the input video signal, according to an instruction from CPU 4. Video output section 34 outputs the vertical synchronizing signal supplied from synchronization switch 35, together with the video display signal, to panel drive circuit 5.
If a vertical synchronizing frequency that can be displayed on display panel 6 is of 60 Hz or lower, then when the vertical synchronizing signal separated from the input video signal has a frequency higher than 60 Hz, video images may not be displayed on display panel 6 in synchronism with the vertical synchronizing signal. With the video display device according to the background art, when the vertical synchronizing signal obtained from the input video signal has a frequency of 60 Hz or lower, video images are displayed on display panel 6 using the vertical synchronizing signal, and when the vertical synchronizing signal obtained from the input video signal has a frequency higher than 60 Hz, video images are displayed on display panel 6 using the panel vertical synchronizing signal (60 Hz) which is asynchronous with the input video signal.
The video display device shown in FIG. 1 successively performs a signal discriminating process for determining the type and resolution of the input video signal, makes image processing settings for an image processing sequence which corresponds to the determined input video signal, and performs a signal monitoring process for monitoring the video signal for changes, for thereby determining the type and resolution of the input video signal without errors and performing an appropriate image processing sequence corresponding to the video signal to display video images.
The signal discriminating process, the image processing settings, and the signal monitoring process performed by the video display device according to the background art shown in FIG. 1 will specifically be described below.
Operation of the video display device according to the background art with respect to an example wherein a computer is used as a video reproducing device, a video signal (RGB signals) output from an external video output terminal of the computer is input to the video display device, and the resolution of the video signal switches from WSXGA+ to WUXGA. Signal specifications of WSXGA+ are shown in Table 1, and signal specifications of WUXGA are shown in Table 2.
TABLE 1WSXGA + (1680 × 1050)Hor Pixels1680PixelsVer Pixels1050LinesHor Frequency64.674KHz15.5mSecVer Frequency59.883Hz16.7nSecPixel Clock119MHz8.4μSecScan TypeNon InterlacedHor Sync PolarityPositiveVer Sync PolarityNegativeHor AddrTime2080Pixels15.462μSecVer Total Time1920Pixels14.118μSecVer AddrTime1080Lines16.235mSecVer Sync Time6Lines0.093mSec
TABLE 2WUXGA (1920 × 1200)Hor Pixels1920PixelsVer Pixels1200LinesHor Frequency74.038KHz16.7mSecVer Frequency59.95Hz8.4nSecPixel Clock154MHz15.5μSecScan TypeNon InterlacedHor Sync PolarityPositiveVer Sync PolarityNegativeHor AddrTime2080Pixels13.506μSecVer Total Time1920Pixels12.468μSecVer AddrTime1080Lines16.699mSecVer Sync Time6Lines0.093mSec
When a video signal of WSXGA+ is input to the video display device, signal discriminating and monitoring circuit 2 performs a signal discriminating process by counting intervals of the horizontal synchronizing signal and the vertical synchronizing signal using a given reference clock signal to measure a horizontal synchronizing frequency (64.674 KHz: error±1% accuracy) and a vertical synchronizing frequency (59.883 Hz: error±0.5% accuracy).
Signal discriminating and monitoring circuit 2 also calculates the total number of lines (1080 Lines: error±1% accuracy) of the video signal from the counts produced by measuring the horizontal synchronizing frequency and the vertical synchronizing frequency, and determines the number of effective video lines of the input video signal based on the calculated total number of lines (1050 Lines).
Furthermore, signal discriminating and monitoring circuit 2 detects a synchronizing polarity (H: Posi, V: Nega), a synchronizing type (Sep), a scan type (Non-Interlaced), and a vertical synchronizing width (6 Lines), and outputs the detected information to CPU 4.
CPU 4 determines the type (RGB signals) and resolution (WSXGA+) of the input video signal from the information detected by signal discriminating and monitoring circuit 2, and determines an aspect ratio 16:10 of displayed images.
At this time, in order to avoid an erroneous determination as to whether or not the input video signal has changed, CPU 4 acquires a plurality of (e.g., five) information (e.g., the horizontal synchronizing frequency) from signal discriminating and monitoring circuit 2 in each processing cycle (e.g., 25 msec.) of CPU 4, and detects a change in the input video signal based on the acquired information. When CPU 4 detects a change in the input video signal, CPU 4 acquires a plurality of (e.g., three) information items from signal discriminating and monitoring circuit 2, and determines the type and resolution of the input video signal that has changed.
When CPU 4 determines the type and resolution of the input video signal, it proceeds to a process of making image processing settings, and supplies parameter values (frequency-dividing ratio and phase for A/D converter 1, resolution converting data for use in scaler circuit 3, an aspect ratio, a color system, etc.) which correspond to the determined type (RGB signals) and resolution (WSXGA+) of the input video signal, to A/D converter 1 and scaler circuit 3.
Thereafter, the video display device proceeds to the signal monitoring process for the input video signal.
According to the signal monitoring process, with the measuring accuracy being set to a range narrower than the measuring accuracy in the signal discriminating process, signal discriminating and monitoring circuit 2 calculates the total number of lines (1080 Lines: error±0.5% accuracy) of the input video signal from the counts produced by measuring the horizontal synchronizing frequency (64.7 KHz: error±0.5% accuracy) and the vertical synchronizing frequency (60 Hz: error±0.25% accuracy) of the input video signal, as with the above signal discriminating process.
CPU 4 acquires, in its processing cycle, the synchronizing polarity (H: Posi, V: Nega), the synchronizing type (Sep), the scan type (Non-Interlaced), and the vertical synchronizing width detected by signal discriminating and monitoring circuit 2, and monitors the type and resolution of the input video signal for a change.
If the input video signal has changed from WSXGA+ to WUXGA, then signal discriminating and monitoring circuit 2 detects the signal change, mutes the displayed image, and proceeds to the signal discriminating process. At this time, if the input video signal has changed, the video display device according to the background art may display a blue image or a logo.
In the signal discriminating process, signal discriminating and monitoring circuit 2 counts intervals of the horizontal synchronizing signal and the vertical synchronizing signal using a given reference clock signal to measure a horizontal synchronizing frequency (74.038 KHz: error±1% accuracy) and a vertical synchronizing frequency (59.95 Hz: error±0.5% accuracy), as with the above process.
Signal discriminating and monitoring circuit 2 also calculates the total number of lines (1235 Lines: error±1% accuracy) of the video signal from the counts of the horizontal synchronizing frequency and the vertical synchronizing frequency, and determines the number of effective video lines of the input video signal based on the calculated total number of lines (1200 Lines).
Furthermore, signal discriminating and monitoring circuit 2 detects a synchronizing polarity (H: Posi, V: Nega), a synchronizing type (Sep), a scan type (Non-Interlaced), and a vertical synchronizing width (6 Lines) of the video signal from the horizontal synchronizing signal and the vertical synchronizing signal, and outputs the detected information to CPU 4.
CPU 4 determines the type (RGB signals) and resolution (WUXGA) of the input video signal from the information detected by signal discriminating and monitoring circuit 2, and determines an aspect ratio 16:10.
At this time, in order to avoid an erroneous determination as to whether or not the input video signal has changed, CPU 4 acquires a plurality of (e.g., five) information (e.g., the horizontal synchronizing frequency) from signal discriminating and monitoring circuit 2 in each processing cycle (e.g., 25 msec.) of CPU 4, and detects a change in the input video signal based on the acquired information. When CPU 4 detects a change in the input video signal, CPU 4 acquires a plurality of (e.g., three) information items from signal discriminating and monitoring circuit 2, and determines the type and resolution of the input video signal that has changed.
When CPU 4 determines the type and resolution of the input video signal, it proceeds to a process of making image processing settings, and supplies parameter values (frequency-dividing ratio and phase for A/D converter 1, resolution converting data for use in scaler circuit 3, an aspect ratio, a color system, etc.) which correspond to the determined type (RGB signals) and resolution (WUXGA) of the input video signal, to A/D converter 1 and scaler circuit 3.
Thereafter, the video display device proceeds to the signal monitoring process for the input video signal to repeat the same process as described above.
Since the plural results detected by signal discriminating and monitoring circuit 2 are used to avoid an erroneous determination, as described above, the time required to determine whether or not the input video signal has changed depends on the stability of the input video signal. Therefore, the video display device according to the background art takes about 1 second to 2 seconds until it determines whether or not the input video signal has changed. As it takes time to determine whether or not the input video signal has changed, the video display device according to the background art takes about 2 seconds to 4 seconds after the input video signal has changed until an image processing sequence, depending on the type and resolution of the input video signal that has changed, is determined. During this time, disturbed video images may be displayed.